On-Chip Inductance Extraction, Simulation and Modeling A THESIS SUBMITTED TO THE FACULTY OF THE GRADUATE SCHOOL OF THE UNIVERSITY OF MINNESOTA BY HAITIAN HU IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF DOCTOR OF PHILOSOPHY

And have found that it is complete and satisfactory in all aspects, and that any and all revisions required by final examining committee have been made. Abstract As technologies shrink further, operating frequencies increase, and low-k dielectrics are introduced to diminish capacitive effects, on-chip inductance effects become more and more dominant in VLSI circuits. The accurate extraction, simulation and modeling of inductance are seen as growing problems in recent years and trends show that the relative contribution of inductive effects will continue to increase. Inductive effects have become important in determining power supply integrity, timing and noise analysis, especially for global clock networks, signal buses and supply grids in upper several layers for high-performance microprocessors. This thesis consists of three parts, covering the extraction, simulation and compact modeling aspects of on-chip inductance issues. The first part deals with the fast and highly accurate simulation of on-chip inductance with precorrected-FFT method that considers all the inductance terms. The second part presents a circuit-aware extraction method that drops some inductance terms and gives out a highly sparsified inverse inductance matrix for the fast and accurate simulation of on-chip inductance system. The last part of this thesis is devoted to building up a compact model for on-chip inductance systems for applications in timing and noise analysis. A precorrected-FFT approach for fast and highly accurate simulation of circuits with on-chip inductance is first proposed. This work is motivated by the fact that circuit analysis and optimization methods based on the partial element equivalent circuit (PEEC) model require the solution of a subproblem in which a dense inductance matrix must be multiplied by a given vector, an operation with a high computational cost. Unlike traditional inductance extraction approaches, the precorrected-FFT method does not attempt to compute the i nductance matrix explicitly, but assumes the entries in the given vector to be the fictitious currents in inductors and enables the accurate and quick computation of this matrix-vector product by exploiting the properties of the inductance calculation procedure. The effects of all of the inductors are implicitly considered in the calculation: faraway inductor effects are captured by representing the conductor currents as point currents on a grid, while nearby inductive interactions are modeled through direct calculation. The grid representation enables the use of the discrete Fast Fourier ii Transform (FFT) for fast magnetic vector potential calculation. The precorrected-FFT method has been applied to accurately simulate large industrial …